/******************************************************************************
 * ----------------------------------------------------------------------------
 * ACA ASSIGNMENT 3: Simulation of MOESI cache coherence
 * Name: Shriram Gurumoorthy
 * GTID: 902535405
 * Email: shriram.g@gatech.edu
 *
 * This file stores the structures and global variables used
 * for simulation
 * ----------------------------------------------------------------------------
 * ***************************************************************************/

#ifndef __GLOBAL_H__
#define __GLOBAL_H__

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

/* Useful Macros */
#define FALSE 0
#define TRUE  1

/* Number of cores used */
#define NUM_CORE 4

/* Cache states */
typedef enum cacheStates
{ Einvalid = 0,
  Eowned,
  Emodified,
  Eexclusive,
  Eshared
}CState;

/* Cache type */
typedef enum cacheType
{ Edm = 1,
  Esa
}CType;

/* Modes of operation */
typedef enum cacheMode
{ Eread = 0,
  Ewrite,
  EbusRd,
  EbusRdX,
  EbusUpgr
}CMode;

/* Structure to hold the cache information*/
typedef struct cacheMemory
{ unsigned int state;
  unsigned int cacheTransfer1;
  unsigned int cacheTransfer2;
  unsigned int cacheTransfer3;
  unsigned int Minvalidation;
  unsigned int Oinvalidation;
  unsigned int Einvalidation;
  unsigned int Sinvalidation;
  unsigned int Iinvalidation;
  unsigned int dirtyWB;
}Cache;

/* Structure needed by processor to hold the info about each intruction */
typedef struct proc
{ unsigned int time;
  int mode;
  unsigned int addr;
  unsigned int valid;
}Processor;

/* Create N processors and N cahces */
Processor P[NUM_CORE];
Cache DMCache[NUM_CORE];
Cache SACache[NUM_CORE];

#endif

